InP BASED HETEROJUNCTION BIPOLAR TRANSISTORS WITH EMITTER-UP AND EMITTER-DOWN PROFILES ON A COMMON WAFER

ABSTRACT

A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.11/052,935, filed on Feb. 7, 2005, and is related to U.S. ProvisionalApplication No. 60/603,480, filed on Aug. 20, 2004 for “Group III-VCompound Semiconductor Based Heterojunction Bipolar Transistors withVarious Collector Profiles on a Common Wafer” by Mary Chen and MarkoSokolich, the disclosure of which is incorporated herein by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

The present invention was made with support from the United StatesGovernment under Grant No. F33615-02-C-1286 awarded by DARPA. The UnitedStates Government has certain rights in the invention.

FIELD

This invention relates to a new design with InP based HeterojunctionBipolar Transistors (HBTs) with emitter-down profiles, including thosefor high Ft HBTs, and emitter-up profiles, including those for highbreakdown voltage (BVceo), on a common wafer and to a method ofproducing the same.

BACKGROUND AND PRIOR ART

InP based HBT Integrated Circuit (IC) technologies have demonstratedgreat potential in high-speed digital and mixed-signal applicationsbecause of superior speed and bandwidth properties over the SiGe basedHBT technology. Although C. R. Bolognesi et al, “Non-blocking collectorInP/GaAs_(0.51)Sb_(0.49)/InP double heterojunction bipolar transistorwith a staggered lined up base-collector junction”, IEEE Electron DeviceLetters, Vol., 20, No. 4, April, 1999, pp. 155-157 suggests that asymmetry of InP/GaAsSb/InP DHBT band structure may have the potentialfor integration of collector-up and emitter-up devices, presentinvention implements selective ion implantation technology forintegration of high Ft HBT (collector-up HBTs) and high BVceo HBT(emitter-up HBTs) on same chip.

SiGe based HBT technology of various collector concentrations availableon the same chip has been described in the prior art. See, for example,G. Freeman et al, “Device scaling and application trends for over 200GHz SiGe HBTs”, 2003 Topical Meetings on Silicon Monolithic IntegratedCircuits in RF Systems, pp. 6-9, Digest of papers. The SiGe based HBTtechnology enables high F_(t) to be traded for high BVceo on the samechip. However, IC designers up to now could not trade high F_(t) forhigh BVceo or vice versa on the same InP.

The ability to provide high F_(t) HBTs and high BVceo HBTs on the samechip is particularly useful in smart Power Amplifiers (PAs) inmillimeter wave image radar. Increased power provides longer distance ofoperation. Smart PAs with digital electronics to control the PAs can berealized by high speed signal processes for regular logic and high BVceo(breakdown voltage) for large swing at output stage. However, presently,when high BVceo HBTs are used in logic circuits lower speed may occur ascompensation due to inability to serve as high F_(t) HBTs in logiccircuits on the same chip.

The ability to provide high F_(t) HBTs and high BVceo HBTs on a commonchip substrate may also be useful in the front-end stage of an analog todigital (A/D) converter. Having high F_(t) HBTs and high BVceo HBTs oncommon chip substrate may provide increased dynamic range and largerinput to analog converter which may be advantageous for highersignal/noise (S/N) ratio and resolution. However, A/D technologies oftoday cannot provide significantly higher peak-to-peak input signal than1V with good linearity. Better dynamic range may improve thistechnology.

Accordingly there is a need for fabricating and integrating high F_(t)HBTs and high BVceo HBTs on the common non-silicon based wafer.

BRIEF DESCRIPTION OF THE FIGURES AND THE DRAWINGS

FIG. 1 depicts a side view of an emitter-up HBT;

FIG. 2 depicts a side view of an emitter-down HBT;

FIG. 3 depicts a wafer with HBTs on the wafer;

FIGS. 4-23 depict a process of forming HBTs based on an exemplaryembodiment;

FIGS. 24-29 depict a process of forming HBTs based on another exemplaryembodiment.

DETAILED DESCRIPTION

In the following description, like reference numbers are used toidentify like elements. Furthermore, the drawings are intended toillustrate major features of exemplary embodiments in a diagrammaticmanner. The drawings are not intended to depict every feature of everyimplementation nor relative dimensions of the depicted elements, and arenot drawn to scale.

The present disclosure describes new designs with InP based HBTs withemitter-up (collector-down) and emitter-down (collector-up) profilesincluding those for high F_(t) HBTs and high BVceo HBTs on a commonwafer. Specially designed epi-taxial layer structures with selectivearea doping by ion implantation can integrate HBTs with emitter-up andemitter-down profiles, including those HBTs for high F_(t) and HBTs forhigh BVceo on the same InP wafer without backside processing.

Referring to FIGS. 1 and 2, in one exemplary embodiment, a cutaway sideview is shown of two out of hundreds of thousands (for example) of HBTs10 and 11 of the presently disclosed technology that may be grown aspart of individual circuits 30 separated by streets 40 on a substrate ofwafer 20 (See FIG. 3). For clarity reasons the HBTs 10 and 11,individual circuits 30 and wafer 20, as depicted in FIGS. 1, 2 and 3,are not to scale.

According to the presently disclosed technology, HBTs, as shown in FIGS.1 and 2, may be grown having either a high BVceo or a high F_(t) byperforming ion implantation in layer 90 or layer 70, as shown in FIGS. 1and 2.

Referring to FIGS. 1-19, individual HBTs 10 and 11 may be grown on thesubstrate 50 of the wafer 20, wherein the substrate layer 50 may be aSemi-Insulating (S.I.) InP wafer. The thickness of the substrate layer50 may be about 0.5 mm. For clarity and example purposes FIGS. 3-19depict the process of forming at least one emitter-up HBT 10 and atleast one emitter-down HBT 11 on the single wafer 20, as shown in FIG.3.

Referring to FIG. 4, layer 60 may be formed, for example by epitaxialgrowth, on top of the substrate 50. The layer 60 may comprise, forexample, N-type InGaAs (N+) material that is heavily doped with siliconor N-type InP (N+) material that is heavily doped with silicon. Thethickness of the layer 60 can vary from about 100 Å to about 5000 Å.Layer 60 may function as a sub-collector layer for emitter-up HBT 10 oras a sub-emitter layer for emitter-down HBT 11.

Referring to FIG. 5, layer 70 may be formed, for example, by epitaxialgrowth, on top of the layer 60. The layer 70 may comprise, for example,N-type InP (N−) undoped material. The thickness of the layer 70 may bedetermined by the emitter-up HBTs in the wafer 20 with the highest BVceorequirement. Layer 70 may be formed uniformly across layer 60 to amaximum thickness that is required to yield the emitter-up HBT with thehighest BVceo requirement. The profile of the layer 70 for emitter-upHBTs may be varied as described in the U.S. Provisional Application No.60/603,480, incorporated herein by reference. Layer 70 may function as acollector layer for emitter-up HBT 10 or as an emitter layer foremitter-down HBT 11.

Referring to FIGS. 2 and 6-11, to form an emitter layer for emitter-downHBT 11, an ion implantation may be performed on layer 70 to createN-type doped (N) regions 75 and isolated regions 78. Isolation regions78 may prevent parasitic current injection through the extrinsicbase-emitter junction area under forward bias. The ion implantation ofregion 75 in the individual emitter-down HBTs 11 may be performed by: 1)applying and forming an implant mask 71 on top of the layer 70 so as toexpose only the portion of the layer 70 for one or more of theemitter-down HBTs, as shown in FIG. 6; 2) performing ion implantationuntil region 75 is formed, as shown in FIG. 7; 3) removing implant mask71 and annealing the structure in FIG. 8 for implant activation anddamage removal wherein N region 75 is formed.

This disclosure is not limited to a shape of implant region 75 asdepicted in FIGS. 2 and 6-8. There may be single or multiple implantsforming individual region 75 depending on the performance requirementsfor the emitter-down HBTs 11. The thickness and doping level of region75 may be formed by varying the energy and dose of the ion implantationprocess.

Referring to FIGS. 2 and 9-11, the ion implantation of regions 78 forisolation in the individual emitter-down HBTs 11 may be performed by: 1)applying and forming an implant mask 72 on top of the layer 70 so as toexpose only the portions of the layer 70 for one or more of theemitter-down HBTs, as shown in FIG. 9; 2) performing ion implantationuntil regions 78 are formed, as shown in FIG. 10; 3) removing implantmask 72, as shown in FIG. 11. This disclosure is not limited to shape ofimplant isolation regions 78 as depicted in FIGS. 2 and 9-11.

The ion implantation of regions 75 may follow ion implantation ofregions 78. If regions 78 are implanted before regions 75, regions 75may be subjected to rapid thermal annealing to avoid possible thermalinstability in regions 78.

The ion implantation of regions 75 and 78 may be performed by regularmasked implantation or by stencil mask ion implantation technology. Seefor example Takeshi Shibata et al, “Stencil mask ion implantationtechnology”, IEEE Transactions on semiconductor manufacturing, Vol, 15,No. 2, May 2002, pp. 183-188.

Upon completion of the ion implantation, an optional smoothing layer(not shown) may be formed by epitaxial growth on top of the layer 70.The smoothing layer may enable smoothing of the epitaxial growth surfaceprior to deposition of the base-collector interface and emitter-baseinterface. The smoothing layer may comprise, for example, N-type InP(N−) material. The thickness of the smoothing layer may, for example, beabout 200 Å.

Referring to FIG. 12, a base layer 80 may be formed, for example, byepitaxial growth, on top of the layer 70 or on top of the optional layerreferred to above. The base layer 80 may comprise, for example, P-typeGaAsSb (P+) material. The thickness of the base layer 80 may, forexample, be about 400 Å.

Referring to FIG. 13, a layer 90 may be formed, for example by epitaxialgrowth, on top of the base layer 80. The layer 90 may comprise, forexample, N-type InP (N) material doped with silicon. The thickness ofthe layer 90 may, for example, be about 1500 Å. Layer 90 may function asan emitter layer for emitter-up HBT 10 or as a collector layer foremitter-down HBT 11.

Referring to FIG. 14, a layer 100 may be formed, for example byepitaxial growth. The emitter cap layer 9 may comprise, for example,N-type InGaAs (N+) material that is doped heavily with silicon. Thethickness of the layer 100 may, for example, be about 1000 Å. Layer 100may function as a collector cap for emitter-down HBT 11 or as an emittercap for emitter-up HBT 10.

Referring to FIG. 1, an optional implantation of region 95 may beperformed to increase doping of the emitter layer (layer 90) and loweremitter resistance Re for emitter-up HBTs 10.

Referring to FIGS. 1 and 15-17, to form an emitter layer for emitter-upHBT 10, an ion implantation may be performed on layer 90 to create aheavily doped (N+) region 95. The ion implantation of region 95 in theindividual emitter-up HBTs 10 may be performed by: 1) applying andforming an implant mask 91 on top of the layer 100 so as to expose onlythe portions of the layers 90 and 100 for one or more of the emitter-upHBTs, as shown in FIG. 15; 2) performing ion implantation until region95 may be formed, as shown in FIG. 16; 3) removing implant mask 91 andperforming rapid thermal annealing of the structure in FIG. 17 forimplant activation and damage removal wherein N+ region 95 may beformed.

Ion implantation of region 95 may be performed on layer 90 prior toformation of layer 100.

This disclosure is not limited to a shape of implant region 95 asdepicted in FIGS. 1 and 15-17. There may be single or multiple implantsforming individual region 95 depending on the performance requirementfor emitter-up HBTs 10. The thickness and doping level of region 95 maybe formed by varying the energy and dose of the ion implantationprocess.

In one exemplary embodiment, the process of HBT fabrication may include:providing metal contacts 110 through lithography and metal deposition asshown in FIG. 18; etching emitter mesas 150 for emitter-up HBT 10 andcollector mesas 160 for emitter-down HBT 11, as shown in FIG. 19;providing base metal contacts 120 through lithography and metaldeposition, as shown in FIG. 20; etching base mesas 170, as shown inFIG. 21; providing metal contacts 130 through lithography and metaldeposition, as shown in FIG. 22; and etching isolation mesas 180, asshown in FIG. 23. As shown in FIGS. 18-23, the substrate 50 has the samethickness at locations under the emitter-up HBT 10 and the emitter-downHBT 11. The substrate 50 may also have the same thickness at locationsbetween the emitter-up HBT 10 and the emitter-down HBT 11.

Metal contacts 110 may function as emitter contacts for emitter-up HBTs10 or as a collector contact for emitter-down HBTs 11. Metal contacts130 may function as collector contacts for emitter-up HBTs 10 or asemitter contacts for emitter-down HBTs 11. The electrically conductingmetal contacts 110, 120, 130 may comprise, for example, Ti/Pt/Au,Pt/Ti/Pt/Au, AuGe or AuGe/Ni/Au.

Referring to FIGS. 24-29, in another exemplary embodiment, the processof HBT fabrication may include formation of self-aligned base metalcontacts 120 so as to lower base resistance. Referring to FIG. 24,formation of self-aligned metal contacts 120 may include providing metalcontacts 110 through lithography and metal deposition. Referring to FIG.25, emitter mesas 210 for emitter-up HBT 10 and collector mesas 220 foremitter-down HBT 11 may be etched. Using metal contacts 110 as a mask,etching of mesas 210 and 220 may be performed. Due to over etching,lateral overhang of the metal contacts 110 may be expected.

Referring to FIG. 26, layer 200 may be formed to at least partiallycover metal contacts 110. Layer 200 may comprise, for example, positivetone photo definable polyimide (PDPI) or positive tone photo sensitiveinterlayer dielectric (ILD).

Referring to FIG. 27, layer 200 may be soft baked, may be flood exposed(maskless) and may be developed so as to remove most of the exposedlayer 200 material except for the portions 201, 202, 203 and 204protected by the lateral overhang of the metal contacts 110. Flooding ofthe layer 200 may be performed with g-line (436 nm) or I-line (365 nm)lithography tools. Portions 201, 202, 203 and 204 may further be curedso as to avoid damage from sequential solvents or other processes.

Referring to FIGS. 28-29, formation of self-aligned metal contacts 120may be performed by: providing a photoresist layer 205 (patterned forbase contact metal) so as to expose portions of layer 80, as shown inFIG. 28; depositing metal contacts 120 and removing photoresist layer205 through lift off process, as shown in FIG. 29; removing any metalflaxes that may be deposited on portions 201, 202, 203, 204 byperforming slight Argon (Ar) ion milling etch process.

The process of HBT fabrication may further include: etching base mesas(not shown); providing metal contacts 130 through lithography and metaldeposition; and etching isolation mesas (not shown).

The foregoing Detailed Description of exemplary and preferredembodiments is presented for purposes of illustration and disclosure inaccordance with the requirements of the law. It is not intended to beexhaustive nor to limit the invention to the precise form(s) described,but only to enable others skilled in the art to understand how theinvention may be suited for a particular use or implementation. Thepossibility of modifications and variations will be apparent topractitioners skilled in the art. No limitation is intended by thedescription of exemplary embodiments which may have included tolerances,feature dimensions, specific operating conditions, engineeringspecifications, or the like, and which may vary between implementationsor with changes to the state of the art, and no limitation should beimplied therefrom. Applicant has made this disclosure with respect tothe current state of the art, but also contemplates advancements andthat adaptations in the future may take into consideration thoseadvancements, namely in accordance with the then current state of theart. It is intended that the scope of the invention be defined by theclaims as written and equivalents as applicable. Reference to a claimelement in the singular is not intended to mean “one and only one”unless explicitly so stated. Moreover, no element, component, nor methodor process step in this disclosure is intended to be dedicated to thepublic regardless of whether the element, component, or step isexplicitly recited in the claims. No claim element herein is to beconstrued under the provisions of 35 U.S.C. Sec. 112, sixth paragraph,unless the element is expressly recited using the phrase “means for . .. ” and no method or process step herein is to be construed under thoseprovisions unless the step, or steps, are expressly recited using thephrase “comprising the step(s) of . . . ”

1. A wafer comprising: an InP based semiconductor substrate; at leastone emitter-up Heterojunction Bipolar Transistor (HBT), wherein acollector layer is disposed between a base layer and a substrate; and atleast one emitter-down HBT, wherein an emitter layer is disposed betweena base layer and a substrate.
 2. The wafer as claimed in claim 1 whereinsaid at least one emitter-down HBT comprises a plurality of ionimplanted regions in said emitter layer.
 3. The wafer as claimed inclaim 2 wherein at least one of said plurality of ion implanted regionsis annealed for doping activation.
 4. The wafer as claimed in claim 2wherein said plurality of ion implanted regions is implanted afterformation of said emitter layer.
 5. The wafer as claimed in claim 1wherein said at least one emitter-up HBT comprises an ion implantedregion in said emitter layer.
 6. The wafer as claimed in claim 5 whereinsaid ion implanted region is annealed for doping activation.
 7. AnIntegrated Circuit (IC) comprising: an InP based semiconductorsubstrate; at least one emitter-up Heterojunction Bipolar Transistor(HBT), wherein a collector layer is disposed between a base layer and asubstrate; and at least one emitter-down HBT, wherein an emitter layeris disposed between a base layer and a substrate.
 8. The IC as claimedin claim 7 wherein said at least one emitter-down HBT comprises aplurality of ion implanted region in said emitter layer.
 9. The IC asclaimed in claim 8 wherein at least one of said plurality of ionimplanted regions is annealed for doping activation.
 10. The IC asclaimed in claim 8 wherein said plurality of ion implanted regions isimplanted after formation of said emitter layer.
 11. The IC as claimedin claim 7 wherein said at least one emitter-up HBT comprises an ionimplanted region in said emitter layer.
 12. The IC as claimed in claim11 wherein said ion implanted region is annealed for doping activation.13. A wafer comprising: at least one emitter-up Heterojunction BipolarTransistor (HBT) comprising: an InP based semiconductor substrate; asub-collector layer formed on said substrate; a collector layer formedon said sub-collector layer; a base layer formed on said collectorlayer; an emitter layer formed on said base layer; an emitter cap layerformed on said emitter layer; an electrically conducting emitter contactformed on said emitter cap layer; an electrically conducting basecontact formed on said base layer; and an electrically conductingcollector contact formed on said sub-collector layer; at least oneemitter-down HBT comprising an InP based semiconductor substrate; asub-emitter layer formed on said substrate; an emitter layer formed onsaid sub-emitter layer; a plurality of implant regions within saidemitter layer; a base layer formed on said emitter layer; a collectorlayer formed on said base layer; a collector cap formed on saidcollector layer; an electrically conducting collector contact formed onsaid collector cap; an electrically conducting base contact formed onsaid base layer; and an electrically conducting emitter contact formedon said sub-emitter layer.
 14. The wafer as claimed in claim 13 whereinat least one of said plurality of ion implanted regions is annealed fordoping activation.
 15. The wafer as claimed in claim 14 wherein saidplurality of ion implanted regions is implanted after formation of saidemitter layer.
 16. The wafer as claimed in claim 13 wherein said atleast one emitter-up HBT comprises an ion implanted region in saidemitter layer.
 17. The wafer as claimed in claim 16 wherein said ionimplanted region is annealed for doping activation.
 18. An integratedcircuit comprising: an emitter-up Hetero junction Bipolar Transistor(HBT) on a first location on a substrate comprising: an undopedcollector layer over the substrate; a base layer over the undopedcollector layer; and an emitter layer over the first portion of the baselayer; and an emitter-down HBT on a second location on the substrate,wherein the substrate is of equal thickness at the first location andthe second location, the emitter-down HBT comprising: a first ionimplant in the undoped collector layer to provide an intrinsic emitter;a second ion implant in the undoped collector layer adjacent to thefirst ion implant to prevent parasitic current injection through anextrinsic base emitter junction area under forward bias; the base layerover the first and second ion implants; and the emitter layer over thebase layer to provide a collector for the emitter-down HBT.
 19. Theintegrated circuit of claim 18 wherein the substrate comprises asemi-insulating InP wafer.
 20. The integrated circuit of claim 18wherein the undoped collector layer comprises N-type InP (N⁻) undopedmaterial.
 21. The integrated circuit of claim 18 wherein a thickness ofthe undoped collector layer is selected to obtain a desired BVceo. 22.The integrated circuit of claim 18 wherein the base layer comprisesP-type GaAsSb (P+) material.
 23. The integrated circuit of claim 18wherein the emitter layer comprises N-type InP (N) material.
 24. Theintegrated circuit of claim 18 wherein the emitter-up HBT furthercomprises a third ion implant in the emitter layer.
 25. The integratedcircuit of claim 18 wherein: the emitter-up HBT further comprises: anemitter mesa; a first base mesa; and a first isolation mesa; and formingthe emitter-down HBT further comprises: a collector mesa; a second basemesa; and a second isolation mesa.
 26. The integrated circuit of claim18 wherein: the emitter-up HBT further comprises: an emitter mesa; anemitter metal contact overhanging the emitter mesa; and a self alignedbase metal contact.
 27. The integrated circuit of claim 18 wherein: thesubstrate comprises a semi-insulating InP wafer; the undoped collectorlayer comprises N-type InP (N⁻) undoped material; the base layercomprises P-type GaAsSb (P+) material; and the emitter layer comprisesN-type InP (N) material.
 28. The integrated circuit of claim 18 wherein:the emitter-up HBT has a high BVceo; and the emitter-down HBT has a highFt.
 29. A method of forming an emitter-up Heterojunction BipolarTransistor (HBT) and an emitter-down HBT on a single wafer, said methodcomprising: providing an InP based semiconductor substrate; forming twoemitter-up HBTs comprising at least a base layer disposed above acollector layer; and converting one of the two emitter-up HBTs into anemitter-down HBT by ion implanting a portion of the collector layer toform a first implant region and a plurality of second implant regions inthe collector layer, and annealing the substrate to convert the firstimplant region into an N first region such that the N first region ofthe collector layer functions as an emitter for the emitter-down HBT,wherein the N first region is at least partially covered by a collectorcontact of the emitter-down HBT.
 30. The method of claim 29 whereinperforming ion implantation of said portion of the collector layercomprises: applying and forming an implant mask to said collector layerto expose only said portion of said collector layer; implanting thefirst implant region in said collector layer.
 31. The method of claim 29further comprises: performing ion implantation on said layer to formthird implant region in said layer.
 32. The method of claim 29 whereinperforming ion implantation of said third implant region comprises:applying and forming an implant mask to said layer to expose only aportion of said layer; implanting said third implant region in saidlayer; and annealing said substrate to convert the third implant regioninto an N third region.
 33. The method of claim 29 further comprising:forming a first metal contact on at least one of the HBTs; forming afirst mesa for the at least one of the HBTs so that said first metalcontact overhangs said first mesa; forming a photo sensitive dielectriclayer to at least partially cover said first metal contact; floodexposing said photo sensitive dielectric layer; developing said photosensitive dielectric layer to remove most of said photo sensitive layer,wherein portions of said photo sensitive dielectric layer remain undersaid overhang of said first metal contact; forming self-aligned metalcontacts.
 34. The method of claim 29 wherein performing ion implantationof said portion of the collector layer comprises: applying and formingan implant mask to said collector layer to expose only the portion ofsaid collector layer; implanting the first implant region in saidcollector layer.
 35. The method of claim 29 wherein performing ionimplantation of said third implant region comprises: applying andforming an implant mask to said layer to expose only a portion of saidlayer; implanting the third implant region in said layer; and annealingsaid substrate to convert the third implant region into an N thirdregion.
 36. The method of claim 29, wherein annealing the substrate isdone before forming the plurality of second implant regions.
 37. Themethod of claim 29, wherein annealing the substrate is done afterforming the first implant region and the plurality of second implantregions.
 38. The method of claim 29, wherein forming two emitter-up HBTscomprises forming a layer above the base layer that functions as anemitter layer for the emitter-up HBT.
 39. The method of claim 29 whereinforming a plurality of layers comprises: forming two emitter-up HBTscomprising at least a base layer disposed above a collector layer; andconverting one of the two emitter-up HBTs into an emitter-down HBT byion implanting a portion of the collector layer to form a first implantregion and a plurality of second implant regions in the collector layer,and annealing the substrate to convert the first implant region into anN first region such that the N first region of the collector layerfunctions as an emitter for the emitter-down HBT, wherein the N firstregion is at least partially covered by a collector contact of theemitter-down HBT.
 40. The method of claim 29, wherein forming twoemitter-up HBTs comprises forming a layer above the base layer thatfunctions as an emitter layer for the emitter-up HBT.
 41. The method ofclaim 29, wherein the first implant region is between the plurality ofsecond implant regions.
 42. The method of claim 29, wherein the firstimplant region is physically contacting at least one of the secondimplant regions.
 43. The method of claim 29, wherein the plurality ofsecond implant regions are at least partially covered by the base layer.44. The method of claim 29, wherein the first implant region and theplurality of second implant regions are associated with the emitter-upHBT that is being converted into the emitter-down HBT.
 45. A method offorming an emitter-up Heterojunction Bipolar Transistor (HBT) and anemitter-down HBT on a wafer, said method comprising: providing an InPbased semiconductor substrate; forming a plurality of layers on saidsubstrate; forming a first metal contact on a top layer of saidplurality of layers for at least one HBT on said substrate; forming afirst mesa so that said first metal contact overhangs said mesa for saidat least one HBT on said substrate; forming a photo sensitive dielectriclayer so as to at least partially cover said first metal contact on saidsubstrate; flood exposing said photo sensitive dielectric layer;developing said photo sensitive dielectric layer so as to remove most ofsaid photo sensitive dielectric layer, wherein portions of said photosensitive dielectric layer remain under said overhang of said firstmetal contact; forming self-aligned metal contacts.